From Inertial Computing
Revision as of 19:51, 9 May 2009 by Aperez (Talk | contribs)

(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search

The VC68040 is an FPGA-implementation of a 68040-based core with full FPU (and mmu if needed) in an Altera Cyclone low-cost CPLD.

The PGA 68030 is 132-pin, and the PGA 68040 is 179-pin,

Of these 179 pins, 32 are dedicated Address Bus lines, and 32 are dedicated Data bus lines, leaving 115 pins remaining. (38 pins for ground, 5 for JTAG, 27 pins for Vcc, etc)

Of these, only approx 44 pins likely need to be mapped, in addition to the 64 address and data lines (which could be multiplexed for further pin reduction), for a total of 108 needed user I/O pins on any prospective FPGA

Based on the above analysis, Altera Cyclone Part numbers which are well-suited are:

  • EP2C20Q240C8N ($43ea@Digikey, 142 User I/O, 18,752 Logic Elements, 240PQFP)
  • EP1C6Q240C8N ($19/ea@Digikey, 185 User I/O, 5,980 Logic Elements, 240PQFP)
  • EP2C8Q208C8N ($19/ea@Digikey, 138 User I/O, 8,256 Logic Elements, 208PQFP)
  • EP2C5Q208C8N ($14/ea@Digikey, 142 User I/O, 4,608 Logic Elements, 208PQFP)

Well-suited Xilinx components are:

The following signal descriptions apply for the remaining pins: (This data was referenced from the Motorola/Freescale MC68040 Users Manual)

  • Transfer Attributes
    • Transfer Type (TT1, TT0)
    • Transfer Modifier (TM2-TM0)
    • Transfer Line Number (TLN1, TLN0)
    • Transfer Size (SIZ1,SIZ0)
    • User-Programmable Attributes (UPA1, UPA0)
    • Read/Write (R/W)
    • Lock (LOCK)
    • Lock End (LOCKE)
    • Cache Inhibit Out (CIOUT)
  • Bus Transfer Control Signals
    • Transfer Start (TS)
    • Transfer In Progress (TIP)
    • Transfer Acknowledge (TA)
    • Transfer Error Acknowledge (TEA)
    • Transfer Cache Inhibit (TCI)
    • Transfer Burst Inhibit (TBI)
  • Snoop Control Signals
    • Snoop Control (SC1, SC0)
    • Memory Inhibit (MI)
  • Arbitration Signals
    • Bus Request (BR)
    • Bus Grant (BG)
    • Bus Busy (BB)
  • Processor Control Signals
    • Cache Disable (CDIS)
    • Reset In (RSTI)
    • Reset Out (RSTO)
  • Interrupt Control Signals
    • Interrupt Priority Level (IPL2-IPL0)
    • Interrupt Pending Status (IPEND)
    • Autovector (AVEC)
  • Status and Clock Signals
    • Processor Status (PST3-PST0)
    • Bus Clock (BCLK)
    • Processor Clock (PCLK)
  • MMU Disable
  • Data Latch Enable
  • Test signals (NO NEED FOR MAPPING)
    • Test Clock (TCK)
    • Test Mode Select (TMS)
    • Test Data In (TDI)
    • Test Data Out (TDO)
    • Test Reset (TRST)