MonteroBus

From Inertial Computing
Revision as of 21:14, 25 October 2008 by Aperez (Talk | contribs)

(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search

AKA ZetaBus

1x PCIe lane, 1x JTAG (included as part of PCIe), 1x LPC (low pin count, ISA compatible), 1x SMBus

- Possibility to break out to regular PCI using TI's XIO2000A PCI translation bridge