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The A1239 will be the most advanced 68030 A1200 trapdoor accelerator, based on a 68030 CPU but with an FPGA-based DDR SDRAM controller, allowing it to use standard DDR memory, with significant board space and pin trace savings.

A traditional, standard non-ddr SDRAM would require somewhere between 500 to 1500 LUTs, and at least 152 User I/O pins to interface both to the host CPU, as well as the cost of a DIMM socket.

Altera gives away an SDRAM controller IP core for its Cyclone line of FPGAs, the least expensive of which, the EP3C5F256C8N, costs $14 each in single quantities, but would require use of 74LVC logic buffers

EP3C5E144C8 Altera Cyclone III 5K 144-EQFP

Full 020s and 030s as well as all 040s and 060s have both 32-bit address and data paths. Both have 3 Function Code signal pins and two Transfer Size signals. The EC020 in the A1200 has a 24-bit address bus.

Folks in #vhdl suggested using a 66-pin TSSOP 64MByte DDR chip such as the Qimonda HYB25D512160CE-5 which is $12 in single quantites, and $8.73 for 25+ from DigiKey. This chip requires 15 (16?) address lines from the 020/030 be mapped (13 true address lines plus one each for RAS/CAS) as well as 16 data lines for the RAM module.

These can then be driven directly from the Cyclone II or III FPGA, and will use half the pins on the memory side.

a 168-pin DIMM uses around 91 active signals which would need to be routed to an FPGA. In contrast, using DDR SDRAM allows the pin count to stay at a comparatively low 42 pins to a 144-pin EQFP Altera Cyclone III FPGA, which has 94 usable I/O pins